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Rail-to-Rail, Fast, Low Power, 2.5 V to 5.5 V, Single-Supply TTL/CMOS Comparators Preliminary Technical Data ADCMP608/ACMP609
FEATURES
10 mV sensitivity rail to rail at VCC = 2.5 V Input common-mode voltage from -0.2 V to VCC + 0.2 V Low glitch CMOS-/TTL-compatible output stage 30 ns propagation delay 1 mW at 2.5 V Shutdown pin Single-pin control for programmable hysteresis and latch Power supply rejection >60 dB -40C to +125C operation
FUNCTIONAL BLOCK DIAGRAMS
NONINVERTING INPUT +
ADCMP608
INVERTING INPUT -
Q OUTPUT
SDN
APPLICATIONS
High speed instrumentation Clock and data signal restoration Logic level shifting or translation High speed line receivers Threshold detection Peak and zero-crossing detectors High speed trigger circuitry Pulse-width modulators Current-/voltage-controlled oscillators
NONINVERTING INPUT
+
Q OUTPUT Q OUTPUT
ADCMP609
INVERTING INPUT -
LE/HYS
SDN
Figure 1.
GENERAL DESCRIPTION
The ADCMP608 and ADCMP609 are fast comparators fabricated on Analog Devices' proprietary XFCB2 process. These comparators are exceptionally versatile and easy to use. Features include an input range from VEE - 0.5 V to VCC + 0.5 V, low noise, TTL-/CMOS-compatible output drivers, and latch inputs with adjustable hysteresis and/or shutdown inputs. The devices offer 30 ns propagation delays driving a 15 pF load with 5 mV overdrive on 350/400 A typical supply current. A flexible power supply scheme allows the devices to operate with a single +2.5 V positive supply and a -0.5 V to +3.0 V input signal range up to a +5.5 V positive supply with a -0.5 V to +6V input signal range. Split input/output supplies, with no sequencing restrictions on the ADCMP609, support a wide input signal range while allowing independent output swing control.
+
The TTL-/CMOS-compatible output stage is designed to drive up to 15 pF with full rated timing specs and to degrade in a graceful and linear fashion as additional capacitance is added. The comparator input stage offers robust protection against large input overdrive, and the outputs do not phase reverse when the valid input signal range is exceeded. High speed latch and programmable hysteresis features are also provided in a unique single-pin control option. The ADCMP608 is available in a tiny 6-lead SC70 package with single-ended output and a shutdown pin. The ADCMP609, available in an 8-lead MSOP package, features a shutdown pin, single pin latch, and hysteresis control.
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2006 Analog Devices, Inc. All rights reserved.
05918-001
ADCMP608/ADCMP609
TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagrams............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Electrical Characteristics............................................................. 3 Absolute Maximum Ratings............................................................ 5 Thermal Resistance ...................................................................... 5 ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions............................. 6 Typical Performance Characteristics ............................................. 7
Preliminary Technical Data
Application Information...................................................................9 Power/Ground Layout and Bypassing........................................9 TTL-/CMOS-Compatible Output Stage.........................................9 Using/Disabling the Latch Feature..............................................9 Optimizing Performance..............................................................9 Comparator Propagation Delay Dispersion ........................... 10 Comparator Hysteresis .............................................................. 10 Crossover Bias Point .................................................................. 11 Minimum Input Slew Rate Requirement ................................ 11 Typical Application Circuits ......................................................... 12 Timing Information ....................................................................... 13
REVISION HISTORY
2/06--Revision PrA: Preliminary Version
Rev. PrA | Page 2 of 16
Preliminary Technical Data SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VCCI = VCCO = 3.3 V, TA = 25C, unless otherwise noted. Table 1.
Parameter DC INPUT CHARACTERISTICS Voltage Range Common-Mode Range Differential Voltage Offset Voltage Bias Current Offset Current Capacitance Resistance, Differential Mode Resistance, Common Mode Active Gain Common-Mode Rejection Symbol VP, VN Conditions VCC = 2.5 V to 5.5 V VCC = 2.5 V to 5.5 V VCC = 2.5 V to 5.5 V
ADCMP608/ADCMP609
Min -0.5 -0.2 -5.0 -2.0 -0.5
Typ
Max VCC + 0.5 V VCC + 0.2 V VCC +5.0 +2.0 +0.5
Unit V V V mV A A pF k k dB dB dB mV
VOS IP, IN CP, CN 0.1 V to VCC -0.5 V to VCC + 0.5 V AV CMRR VCCI = 2.5 V, VCCO = 2.5 V, VCM = -0.2 V to 2.7 V VCCI = 5.5 V, VCCO = 5.5 V, VCM = -0.2 V to 5.7 V RHYS =
1 TBD 150 100 80 50 60 0.1
Hysteresis LATCH ENABLE PIN CHARACTERISTICS ADCMP609 only VIH VIL LIH IOL HYSTERESIS MODE AND TIMING Hysteresis Mode Bias Voltage Minimum Resistor Value Latch Setup Time Latch Hold Time Latch to Output Delay Latch Minimum Pulse Width SHUTDOWN PIN CHARACTERISTICS VIH VIL IIH IOL Sleep Time Wake-Up Time DC OUTPUT CHARACTERISTICS Output Voltage High Level Output Voltage Low Level
Hysteresis is shut off Latch mode guaranteed VIH = VCCO + 0.2 V VIL = 0.4 V Current sink 0 A Hysteresis = 60 mV VOD = 100 mV VOD = 100 mV VOD = 100 mV VOD = 100 mV Comparator is operating Shutdown guaranteed VIH = VCC VIL = 0 V ICC < 100 A VOD = 10 mV, output valid VCCO = 2.5 V to 6 V IOH = 1.6 mA VCCO = 2.5 V IOL = 1.6 mA VCCO = 2.5 V
2.0 -0.2
0.4
VCCO + 0.2 0.8 0.1 -0.1 1.35
V V mA mA V k ns ns ns ns V V mA mA ns ns V V
1.08 60
1.25 15 20 20 20
tS tH tPLOH, tPLOL tPL
2.0 -0.2
0.4
VCC 0.6 0.05 -0.05
tSD tH VOH VOL
0.6 3 VCC - 0.4 0.4
Rev. PrA | Page 3 of 16
ADCMP608/ADCMP609
Parameter AC PERFORMANCE Propagation Delay, CL = 15 pF Symbol tPD Conditions VCCI = VCCO = 2.5 V to 5.5 V VCCO = 5.5 V to 2.5 V, VOD = 10 mV VCCO = 2.5 V/5.5 V, VOD = 200 mV VOD = 10 mV 10 mV < VOD < 500 mV 10 V/s to 0.1 V/ns 200 mV p-p single ended VOD 1.25 V, 50 V/s, VCM = 1.25 V VCM = 0 V to VCC 200 m p-p single ended >50% output swing CL = 15 pF VCCI = 5 V VOD = 200 mV, 5 V/ns tPD/PW < 500 ps 10% to 90% CLOAD = 15 pF, VCCI = 2.5 V to 5 V 10% to 90% CLOAD = 15 pF, VCCI = 2.5 V to 5 V Min
Preliminary Technical Data
Typ 30 25/30 2 4 1 1 0.5 TBD TBD 35 25 to 40 25 to 40 Max Unit ns ns ns ns ns ns ns Mbps ns ns ns ns
Propagation Delay Skew--Rising to Falling Transition Overdrive Dispersion Slew Rate Dispersion Small Signal 10% - 90% Duty Cycle Dispersion Common-Mode Dispersion Toggle Rate RMS Random Jitter Minimum Pulse Width Rise Time Fall Time RJ PWMIN tR tF
POWER SUPPLY Input Supply Voltage Range Output Supply Voltage Range Positive Supply Differential (ADCMP609) Positive Supply Differential (ADCMP609) Positive Supply Current Positive Supply Current Input Section Supply Current (ADCMP609) Output Stage Supply Current (ADCMP609) Power Dissipation Shutdown Current Power Supply Rejection
VCCI VCCO VCCI - VCCO Operating VCCI - VCCO Nonoperating IVCC IVCC IVCCi IVCCO PD ISD PSRR VCC = 2.5 V VCC = 5.5 V VCCI = 2.5 V VCCO= 2.5 V VCC = 2.5 V VCC =2.5 V to 5.5 V VCCI = 2.5 V to 5 V
2.5 2.5 -3 -5.5 400 500 270 130 1 50 >50 dB
5.5 5.5 +3 +5.5
V V V V A A mA mA mW A dB
Rev. PrA | Page 4 of 16
Preliminary Technical Data ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Supply Voltages Input Supply Voltage (VCCI to GND) Output Supply Voltage (VCCO to GND) Positive Supply Differential (VCCI - VCCO) Input Voltages Input Voltage Differential Input Voltage Maximum Input/Output Current Shutdown Control Pin Applied Voltage (HYS to GND) Maximum Input/Output Current Latch/Hysteresis Control Pin Applied Voltage (HYS to GND) Maximum Input/Output Current Output Current Temperature Operating Temperature, Ambient Operating Temperature, Junction Storage Temperature Range Rating -0.5 V to +6.0 V -0.5 V to +6.0 V -6.0 V to +6.0 V
ADCMP608/ADCMP609
Stress above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
THERMAL RESISTANCE
-0.5 V to VCCI + 0.5 V (VCCI + 0.5 V) 50mA -0.5 V to Vcco + 0.5 V 50 mA -0.5 V to VCCO + 0.5 V 50 mA 50 mA -40C to +125C 150C -65C to +150C
JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 3. Thermal Resistance
Package Type ADCMP608 SC70 6-lead ADCMP609 MSOP 8-lead
1
JA 1 426 130
Unit C/W C/W
Measurement in still air.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. PrA | Page 5 of 16
ADCMP608/ADCMP609
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Q1
6
Preliminary Technical Data
VCC SDN
05918-002
VCC 1 VP 2 VN 3 SDN 4
8
Q Q
05918-003
ADCMP608
VEE 2 VP 3 TOP VIEW (Not to Scale)
5 4
ADCMP609
TOP VIEW (Not to Scale)
7 6 5
VEE LE/HYS
VN
Figure 2. ADCMP608 Pin Configuration
Figure 3. ADCMP609 Pin Configuration
Table 4. ADCMP608 Pin Function Descriptions
Pin No. 1 2 3 4 5 6 Mnemonic Q VEE VP Vn SDN VCC Description Noninverting Output. Q is at logic high if the analog voltage at the noninverting input, VP, is greater than the analog voltage at the inverting input, VN. Negative Supply Voltage. Noninverting Analog Input. Inverting Analog Input. Shutdown. Drive this pin low to shutdown the device. VCC Supply.
Table 5. ADCMP609 Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 Mnemonic VCCI/VCCO VP Vn SDN LE/HYS VEE Q Q Description Vcc Supply. Noninverting Analog Input. Inverting Analog Input. Shutdown. Drive this pin low to shutdown the device. Latch/Hysteresis Control. Bias with resistor or current source for hysteresis; drive TTL low to latch. Negative Supply Voltage. Noninverting Output. Q is at logic low if the analog voltage at the noninverting input, VP, is greater than the analog voltage at the inverting input, VN, provided the comparator is in compare mode. Inverting Output. Q is at logic high if the analog voltage at the noninverting input VP is greater than the analog voltage at the inverting input, VN, provided the comparator is in compare mode.
Rev. PrA | Page 6 of 16
Preliminary Technical Data TYPICAL PERFORMANCE CHARACTERISTICS
VCCI = VCCO = 3.3 V, TA = 25C, unless otherwise noted.
ADCMP608/ADCMP609
Figure 4. Propagation Delay vs. Input Overdrive
Figure 7. Hysteresis vs. Vcc
Figure 5. Propagation Delay vs. Input Common Mode
Figure 8. Hysteresis vs. RHYS Control Resistor
Figure 6. Propagation Delay vs. Temperature
Figure 9. Input Bias Current vs. Input Common Mode
Rev. PrA | Page 7 of 16
ADCMP608/ADCMP609
Preliminary Technical Data
Figure 10. Input Bias Current vs. Temperature
Figure 12 Latch/Hysteresis Control Pin I/V Characteristic.
Figure 11. Input Offset Voltage vs. Temperature
Rev. PrA | Page 8 of 16
Preliminary Technical Data APPLICATION INFORMATION
POWER/GROUND LAYOUT AND BYPASSING
The ADCMP608 and ADCMP609 comparators are high speed devices. Despite the low noise output stage, it is essential to use proper high speed design techniques to achieve the specified performance. Because comparators are uncompensated amplifiers, feedback in any phase relationship is likely to cause oscillations or undesired hysteresis. Of critical importance is the use of low impedance supply planes, particularly the output supply plane (VCCO) and the ground plane (GND). Individual supply planes are recommended as part of a multilayer board. Providing the lowest inductance return path for switching currents ensures the best possible performance in the target application. It is also important to adequately bypass the input and output supplies. A 0.1 F bypass capacitor should be placed as close as possible to each VCC supply pin. The capacitor should be connected to the GND plane with redundant vias placed to provide a physically short return path for output currents flowing back from ground to the VCC pin. High frequency bypass capacitors should be carefully selected for minimum inductance and ESR. Parasitic layout inductance should also be strictly controlled to maximize the effectiveness of the bypass at high frequencies.
ADCMP608/ADCMP609
VLOGIC
A1
Q1
+IN -IN AV
OUTPUT
A2
Q2
05918-012
GAIN STAGE
OUTPUT STAGE
Figure 13. Simplified Schematic Diagram of TTL/CMOS-COMPATIBLE Output Stage
USING/DISABLING THE LATCH FEATURE
The latch input of the ADCMP609 is designed for maximum versatility. It can safely be left floating or pulled to TTL high for normal comparator operation with no hysteresis, or it can be driven low by any standard TTL/CMOS device as a high speed latch. In addition, the pin can be operated as a hysteresis control pin with a bias voltage of 1.25 V nominal and an input resistance of approximately 7000 . This allows the comparator hysteresis to be easily and accurately controlled by either a resistor or an inexpensive CMOS DAC. Hysteresis control and latch mode can be used together if an open drain, a collector, or a three-state driver is connected in parallel to the hysteresis control resistor or current source. Due to the programmable hysteresis feature,the logic threshold of the latch pin is approximately 1.1 V regardless of VCC.
TTL-/CMOS-COMPATIBLE OUTPUT STAGE
Specified propagation delay performance can be achieved only by keeping the capacitive load at or below the specified minimums. The outputs of the ADCMP608 and ADCMP609 are designed to directly drive one Schottky TTL or three low power Schottky TTL loads or equivalent. For large fan outs, buses, or transmission lines, an appropriate buffer should be used to maintain the excellent speed and stability of the part. With the rated 15 pF load capacitance applied, even at 2.5 V VCC, more than half of the total device propagation delay is output stage slew time. Because of this, the total prop delay will decrease as VCCO decreases and instability in the power supply may show up as excess delay dispersion. This delay is measured to the 50% point for whatever supply is in use, so the fastest times will be observed with the VCC supply at 2.5 V, and larger values will be observed when driving loads, that switch at other levels. Overdrive and input slew rate dispersions are not significantly affected by output loading and VCC variations. The TTL/CMOS-compatible output stage is shown in the simplified schematic diagram of Figure 12. Because of its inherent symmetry and generally good behavior, this output stage is readily adaptable for driving various filters and other unusual loads.
OPTIMIZING PERFORMANCE
As with any high speed comparator, proper design and layout techniques are essential for obtaining the specified performance. Stray capacitance, inductance, common power and ground impedances, or other layout issues can severely limit performance and often cause oscillation. The source impedance should be minimized as much as is practicable. High source impedance, in combination with the parasitic input capacitance of the comparator, will cause an undesirable degradation in bandwidth at the input, thus degrading the overall response. Higher impedances encourage undesired coupling.
Rev. PrA | Page 9 of 16
ADCMP608/ADCMP609
COMPARATOR PROPAGATION DELAY DISPERSION
The ADCMP608 and ADCMP609 comparator is designed to reduce propagation delay dispersion over a wide input overdrive range of 5 mV to VCCI - 1 V. Propagation delay dispersion is the variation in propagation delay that results from a change in the degree of overdrive or slew rate (how far or how fast the input signal exceeds the switching threshold). Propagation delay dispersion is a specification that becomes important in high speed, time-critical applications, such as data communication, automatic test and measurement, and instrumentation. It is also important in event-driven applications, such as pulse spectroscopy, nuclear instrumentation, and medical imaging. Dispersion is defined as the variation in propagation delay as the input overdrive conditions are changed (see Figure 14 and Figure 15). ADCMP608 and ADCMP609 dispersion is typically <5 ns as the overdrive varies from 5 mV to 500 mV, and the input slew rate varies from 2 V/ns to 10 V/ns. This specification applies to both positive and negative signals because the device has very closely matched delays for both positive-going and negativegoing inputs, and very low output skews. Remember to add the actual device offset to the overdrive for repeatable dispersion measurements.
500mV OVERDRIVE
Preliminary Technical Data
COMPARATOR HYSTERESIS
The addition of hysteresis to a comparator is often desirable in a noisy environment, or when the differential input amplitudes are relatively small or slow moving. The transfer function for a comparator with hysteresis is shown in Figure 16. As the input voltage approaches the threshold (0.0 V, in this example) from below the threshold region in a positive direction, the comparator switches from a low to a high when the input crosses +VH/2. The new switching threshold becomes -VH/2. The comparator remains in the high state until the threshold -VH/2 is crossed from below the threshold region in a negative direction. In this manner, noise or feedback output signals centered on 0.0 V input cannot cause the comparator to switch states unless it exceeds the region bounded by VH/2.
OUTPUT
VOH
VOL
-VH 2
0
+VH 2
Figure 16. Comparator Hysteresis Transfer Function
INPUT VOLTAGE 10mV OVERDRIVE VN VOS
Q/Q OUTPUT
Figure 14. Propagation Delay--Overdrive Dispersion
INPUT VOLTAGE 1V/ns VN VOS 10V/ns
05918-013
DISPERSION
The customary technique for introducing hysteresis into a comparator uses positive feedback from the output back to the input. One limitation of this approach is that the amount of hysteresis varies with the output logic levels, resulting in hysteresis that is not symmetric about the threshold. The external feedback network can also introduce significant parasitics that reduce high speed performance, and can even induce oscillation in some cases. The ADCMP609 comparator offers a programmable hysteresis feature that significantly improves accuracy and stability. Connecting an external pull-down resistor or a current source from the LE/HYS pin to GND, varies the amount of hysteresis in a predictable and stable manner. Leaving the LE/HYS pin disconnected or driving it high removes the hysteresis. The maximum hysteresis that can be applied using this pin is approximately 160 mV. Figure 17 illustrates the amount of hysteresis applied as a function of external resistor value. Figure TBD illustrates hysteresis as a function of current.
Q/Q OUTPUT
Figure 15. Propagation Delay--Slew Rate Dispersion
05918-014
DISPERSION
Rev. PrA | Page 10 of 16
05918-015
INPUT
Preliminary Technical Data
The hysteresis control pin appears as a 1.25 V bias voltage seen through a series resistance of 7k 20% throughout the hysterisis control range. The advantages of applying hysteresis in this manner are improved accuracy, improved stability, reduced component count, and maximum versatility. An external bypass capacitor is not recommended on the HYS pin because it would likely degrade the jitter performance of the device and impair the latch function. As described in Using/Disabling the Latch Feature, hysteresis control need not compromise the latch function.
ADCMP608/ADCMP609
CROSSOVER BIAS POINT
Rail-to-rail inputs of this type, in both op amps and comparators have a dual front-end design. Certain devices are active near the VCC rail and others are active near the VEE rail. At some predetermined point in the common-mode range, a crossover occurs. At this point, normally VCC/2, the direction of the bias current reverses and there are changes in measured offset voltages and currents. With VCC less than 4 V, this crossover is at the expected VCC/2, but with VCC greater than 4 V, the crossover point instead follows VCC 1:1, bringing it to approximately 3 V with VCC at 5 V. This means that the comparator input characteristics will more closely resemble the inputs of non rail-to rail ground sensing comparators such as the AD8611.
MINIMUM INPUT SLEW RATE REQUIREMENT
(Remove if device is stable.) As with most high speed comparators, without hysteresis a minimum slew rate must be met to ensure that the device does not oscillate as the input signal crosses the threshold. This oscillation is due to the high gain bandwidth of the comparator in combination with feedback parasitics inherent in the package and PC board. A minimum slew rate of TBD. V/s ensures clean output transitions from the ADCMP608/ADCMP609 comparators without hysteresis. In many applications, chattering is not harmful.
Figure 17. Hysteresis vs. RHYS Control Resistor
Rev. PrA | Page 11 of 16
ADCMP608/ADCMP609
TYPICAL APPLICATION CIRCUITS
Preliminary Technical Data
2.5V
ADCMP608
INPUT 1.25V 50mV
CMOS PWM OUTPUT
2.5V TO 5V 0.1F INPUT 2k
INPUT 1.25V REF
10k 10k
ADCMP609
2k
ADCMP608
OUTPUT
05918-017
10k
220pF
LE/HYS
05918-020
0.1F
100k
Figure 18. Self-Biased 50% Slicer
Figure 21. Oscillator and Pulse Width Modulator
5V
CMOS VDD 2.5V TO 5V
INPUT
10k
+ OUTPUT -
05918-021
ADCMP609
VREF 0.1F LE/HYS
0.02F 10k
LVDS
100
ADCMP608
OUTPUT
05918-018
Figure 19. LVDS to CMOS Receiver
5V 20k 39k
Figure 22. Duty Cycle to Differential Voltage
2.5V TO 5V
ADCMP609
ADCMP609
39k 470pF LE/HYS
OUTPUT
DIGITAL INPUT
05918-019
74AHC 1G07
LE/HYS
150k
150k
HYSTERESIS CURRENT
10k
Figure 20. Voltage Controlled Oscillator
Figure 23. DAC Hysteresis Adjustment with Latch
Rev. PrA | Page 12 of 16
05918-022
CONTROL VOLTAGE 0V TO 2.5V
Preliminary Technical Data TIMING INFORMATION
ADCMP608/ADCMP609
Figure 24 illustrates the ADCMP608/ADCMP609 latch timing relationships. Table 6 provides definitions of the terms found in the figure.
1.1V LATCH ENABLE
tS tH
tPL
DIFFERENTIAL INPUT VOLTAGE
VIN VOD
VN VOS
tPDL
Q OUTPUT
tPLOH
50%
tPDH
tF
50%
Q OUTPUT
tR
Figure 24. System Timing Diagram
Table 6. Timing Descriptions
Symbol tPDH tPDL tPLOH tPLOL tH tPL tS tR tF VOD Timing Input to output high delay Input to output low delay Latch enable to output high delay Latch enable to output low delay Minimum hold time Minimum latch enable pulse width Minimum setup time Output rise time Output fall time Voltage overdrive Description Propagation delay measured from the time the input signal crosses the reference ( the input offset voltage) to the 50% point of an output low-to-high transition. Propagation delay measured from the time the input signal crosses the reference ( the input offset voltage) to the 50% point of an output high-to-low transition. Propagation delay measured from the 50% point of the latch enable signal low-to-high transition to the 50% point of an output low-to-high transition. Propagation delay measured from the 50% point of the latch enable signal low-to-high transition to the 50% point of an output high-to-low transition. Minimum time after the negative transition of the latch enable signal that the input signal must remain unchanged to be acquired and held at the outputs. Minimum time that the latch enable signal must be high to acquire an input signal change. Minimum time before the negative transition of the latch enable signal occurs that an input signal change must be present to be acquired and held at the outputs. Amount of time required to transition from a low to a high output as measured at the 20% and 80% points. Amount of time required to transition from a high to a low output as measured at the 20% and 80% points. Difference between the input voltages VA and VB.
Rev. PrA | Page 13 of 16
05918-023
tPLOL
ADCMP608/ACMP609 NOTES
Preliminary Technical Data
Rev. PrA | Page 14 of 16
Preliminary Technical Data NOTES
ADCMP608/ADCMP609
Rev. PrA | Page 15 of 16
ADCMP608/ACMP609 NOTES
Preliminary Technical Data
(c)2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR05918-0-2/06(PrA)
Rev. PrA | Page 16 of 16

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